Kirvy Teo
Published

Optimizing an FPGA HLS Design with FPGA Tool Settings

Generated RTL code from a C-to-RTL tool is not easy to understand. Here is how to increase design performance without changing any RTL.

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Optimizing an FPGA HLS Design with FPGA Tool Settings

Things used in this project

Software apps and online services

InTime
Plunify Cloud InTime
Xilinx HLS

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Credits

Kirvy Teo

Kirvy Teo

2 projects • 10 followers
I am the founder of Plunify, a company focus on accelerating chip design using machine learning and analytics.

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